Serial data-and control-bus with distribution voltage

ABSTRACT

A bus system for the serial transmission of digital data with a multiplicity of individual addressable bus transceivers (BT), which are connected by an only two-wire common bus, via which both synchronising signals and also digital data and energy are exchanged between the BTs. As the value of a bit, The result of an elementary logical operation (AND or OR) on the values of all simultaneously transmitting BTs with the same address is transmitted to all the receiving BTs with the same address simultaneously. Each BT includes its own time control and synchronising circuit with a time base, a bit counter, a byte counter and a comparator. With an identity between the imprinted address and that appearing on the bus a byte of digital data is transmitted serially via an I/O port The bus system can be put into operation and operated without the use of software, whereby polarisation errors in installation are excluded.

The present invention relates to a bus system for the transmission ofdigital test data or control commands. Several such bus systems areknown and differentiate themselves from each other by the type oftransmission, the addressing, the number of conductors and the energytransmitted.

A large major group of bus systems are concerned with the paralleltransmission of data. They are not considered further here, since theyare not relevant with regard to the present invention. The second largemajor group works with serial transmission of the data and representsthe state of the technology.

In the narrow sense, the state of the technology is formed from systemsin which a multiplicity of participants of an active or passive nature(so-called Bus-Transceivers, BT) are connected to the actual data bus.

Such bus systems are known, for instance, from EP 0 146 045 A2(henceforth D1), U.S. Pat. No. 4,497,391 (henceforth D2), EP 0 540 449A1 (henceforth D3) and EP 0 728 621 A2 (henceforth D4).

D1 describes a carrier frequency system in which a normal electronicsupply conductor is used as the data bus. In D2, a lift control isdescribed that connects on one side the stationary selector stations, onthe other the selector station in the lift via two four-wire systems—inthe sense of the definition chosen here of all Bus Transceivers(BT)—with the actual lift controller or main station. The addressing iseffected by means of a time slot system, wherein each BT is allocated acertain time-defined address twice in each address cycle, the first timefor the transmission of signals from BT to the main station and thesecond time for the reverse direction.

From D3, a fast data connection system is known essentially forapplication in and by computer systems. The system of D3 is especiallyoptimised for high transmission speeds. The data transmission of each BTis effected separated in time according to sending and receiving; evenso, a multiplicity of conductors are provided for the data bus.

The multiplicity of conductors are always brought together in pairs forthe formation of a differential signal.

Further, a bus system developed for application in motor vehicles isknown from D4. The bus system of D3 has a data transmission based onpulse height selection, whereby the transmitted information is encodedusing pulse width modulation and has a higher voltage level than thesupply voltage of the single wire bus system. The zero reference voltageis essentially the potential of the vehicle chassis as the returnconductor to the battery. A further feature in accordance with theinvention is the trapezoidal type current pulse shape for the reductionof discontinuous transitions.

Each of the four systems listed here as examples has its owncharacteristics and is designed for special applications. The use of onesystem in the typical application area of another generally leads togreat difficulties. Further, in all the documents quoted, systems arepresented, which—including the power supply—require at least threeconductors and in all cases have BT installed by specialists (whichnonetheless does not exclude installation faults; see D2).

An aim addressed by the present invention is provision of a bus systemfor serial transmission of digital data with a multiplicity of singleaddressable BTs. The multiplicity of single addressable BTs areconnected by only one two wire common bus. The one two wire common buscan provide the energy supply of the BTs as well as the users connectedto them at any time. It is possible with the one two wire common bustotransmit from precisely one transmitting BT simultaneously to two ormore receiving BTs and to transmit the result of a logical elementoperation, that is the current logical sum (OR Gate) or the currentlogical product (AND Gate), of the digital data from two or moresimultaneously transmitting BTs, simultaneously to one or more or evenseveral receiving BTs at the same time. This bus system can thereby beset into operation and operated without the use of software andadditionally can be designed such that polarity errors are excluded.

Shown are:

FIG. 1 a representation of the principles of the bus system inaccordance with the invention,

FIG. 2 a spatial grouping of the BT in accordance with the invention,

FIG. 3 the block circuit diagram of a master BT 1,

FIG. 4 the block circuit diagram of a slave BT 5,

FIG. 5 the block circuit diagram of a modification of the slave BT 5with reversed polarity protection,

FIG. 6 the voltage curve against time between the two conductors 2, 3 ofthe bus 4 during transmission of a normal data bit,

FIG. 7 the voltage curve against time between the two conductors 2, 3 ofthe bus 4 during transmission of the last data bit of a cycle with asynchronising signal S,

FIG. 8 the block circuit diagram of a form of construction of the BT inaccordance with the invention with an I/O port,

FIG. 9 the detailed circuit diagram of a BT in the function of Master BT1, FIG. 10 the detailed circuit diagram of a BT in the function of SlaveBT 5.

Since the different forms of construction of the functional groupsapplied here are known and familiar to every specialist, these are onlyspecified in detail in individual cases to the level of elementary basiccircuit elements.

In FIG. 1, a representation is shown of principles of the bus system inaccordance with the invention. A master BT 1 is connected to a directcurrent voltage source 9 with a voltage Uo and delivers both electricalenergy and timing information to a bus 4 comprising two conductors 2, 3.A multiplicity of slave BTs 5 are connected in parallel to the bus 4.The two conductors 2, 3 can comprise two individual wires, but also cancomprise one wire and a metal chassis of a vehicle. Each BT has itsaddress stored in coded form. At least two BTs always have the sameaddress.

FIG. 2 shows schematically a spatial grouping of the BT in accordancewith the invention. For instance, a main mounting board 6 and asubsidiary mounting board 7 are provided. The BTs arranged on a mountingboard 6, 7 or otherwise accessible to the user are as a rule connectedto input equipment, such as keys or switches, or to monitors to indicatetest values or conditions, etc. . . Other BTs, which as a rule are notimmediately accessible to the user, are connected to actuators,switches, sensors or similar items.

The BTs discharge monitoring, measurement, and control functions. Theytransmit digital coded information, such as INPUT/OUTPUT conditions,test values, or control commands. Each of the BT that are notimmediately accessible is as a rule a BT on the main mounting board 6and, for instance in a selection therefrom, allocated to a BT on thesubsidiary mounting board 7. Allocated means, that these BTs areimplanted with the same address. Each BT can, if required, be configuredeither as a transmitter or a receiver, as explained in more detailbelow.

FIG. 3 shows a block circuit diagram of a master BT 1. On the conductor2 of the pair of conductors 2, 3 lies a direct current source 8, whichlies on the direct current voltage source 9 with voltage Uo. The secondconductor 3 lies at the null potential. A switch 10 is realised byelectronic means connects, under the influence of the time control 11,for each individual data bit to be transmitted, sequential connectionsPo, Do and Eo to the conductor 2. The pole Po is fixed constantly at thenull potential. As long as the conductor 2 is joined to the pole Po, thetwo conductors 2, 3 are thus effectively short circuited, whereby apause signal P with the value 0 is applied to the bus 4.

A further switch 12, also realised by electronic means, determines thepotential on which the pole Do lies. If a data bit with the value 0 isto be transmitted at a specified point in time from the master BT(whichis configured as a transmitter), the switch 12 is closed and theconnection Do lies at the null potential. The two conductors 2, 3 of thebus 4 are thereby short circuited. If, on the other hand, the master BT1 is configured, for the current bit, as a receiver, the switch 12remains open and the master accepts the value of the bit on the bus 4.

During the period of a data signal D following the pause signal P, thetwo conductors 2, 3 are thus similarly short circuited, in as much as adata bit with the value 0 is transmitted from the master BT 1. Thedirect current source 8, which for greater interference suppressiondelivers a relatively high current i in the order of magnitude of, forinstance, 100 mA, determines the idle potential on the conductor 2during the switch position Do. If a data bit with the value 1 is to betransmitted, the conductor 2 is not short circuited. The direct currentsource 8 pulls the conductor 2, after any loading capacities have beenreversed in charge, to the potential of the direct current voltagesource 9. Following on the data signal D, the conductor 2 is connectedto the pole Eo, which is connected to the positive pole of the directcurrent voltage source 9. The voltage Uo lies on the conductor 2, whichcorresponds to an energy signal E on the bus 4, or a synchronisingsignal S, which will be discussed in more detail below. The conductivityof the conductors 2, 3 must obviously be matched to the current strengthselected for the individual application.

FIG. 4 shows the block circuit diagram of a slave BT 5. Instead of theswitch 12 as in the master BT 1, a corresponding switch 13 is present,similarly achieved by electronic means. If, at a given point in time, adata bit with the value 0 is to be transmitted from a slave BT 5configured as a transmitter, the switch 13 is closed. The pair ofconductors 2, 3 of the bus 4 are thereby short circuited. If, on theother hand, the slave BT 5 is configured as a receiver, this switch 13remains permanently open, and the slave BT 5 accepts the value of thebit on the bus 4 at that point of time. If the value of the applied bitis equal to 1, the current I of the direct current source 8 is led tothe energy storage element 38 described below.

The slave BT 5 includes such an energy storage element 38, which isrealised in that the conductor 2 of the bus 4 is connected to a diode 14in its conducting direction and whose output is applied to a storagecapacitor 15. If an energy signal E or a synchronising signal S isapplied to the conductor 2, the storage capacitor 15 is charged. Astabiliser 16 similarly attached to this storage capacitor 15 delivers astabilised voltage of, for instance 5V, at its output. The stabiliser 16is used to feed the slave BT 5 as well as to supply the load connectedto this slave BT 5. Obviously, a direct energy supply to the slave BT 5would be possible. For this purpose, however, an additional two wirefeeder from a source of electrical energy to the slave BT 5 would haveto be installed. A substantial advantage of the invention, namely, thatthe energy for each BT and each load connected to it is also deliveredvia the bus, would thereby be unused.

If now only one of the various mutually allocated BTs closes its switch13, or the switch 12 in the case of the master BT 1, the bus is shortcircuited, which in positive logic corresponds to a logical product(i.e., a wired logical AND gate or “wired AND”). All the switches 13, or12, of all the BTs connected with the same address must be open, so thata positive voltage(i.e., a logical 1), appears on the bus 4. If,conversely, also in only one BT with the same address this switch 13, or12, is closed, the bus 4 is short circuited, which in negative logiccorresponds to a logical sum, that is a wired logical OR Gate (“wiredOR”). No voltage(i.e., a logical 0) thereby appears on the bus 4. Thesetwo logical element components make it possible, for instance, to causean effect on the same receiver, for instance a relay, from differentcontrol units.

In FIG. 5, the block circuit diagram of a modification of a slave BT 5is shown, with polarity protection. This modification differs from theversion shown in FIG. 4 only in that the conductors 2, 3 of the bus 4are not joined directly to the slave BT 5, but via a full-wave rectifier17. It is thereby ensured that no polarity errors can arise in theinstallation of the bus system in accordance with the invention.Elimination of potential polarity errors correspondingly eases theinstallation.

FIG. 6 shows the idealised voltage curve between the two conductors 2, 3of the bus 4 during the transmission of a normal data bit. Following thetransmission of a first synchronising signal S by the master BT 1, theBTI acts to place, under the control of its timing control, a cyclicallyrecurring train of identical bits. Each of these bits thereby requires abit-time interval T. This bit-time interval T can be pre-chosen inprinciple as desired within the technical limits. The reciprocal of thebit-time, 1/T is the upper limit of the possible transmission rate usingthe bus system. The number of bits within a cycle is in theory asdesired However, number of bits within the cycle is preferably equal toa power of 2 (i.e., 2^(n)), , such as, for example, 2¹⁰=1024.

Following the completion of these 1024 sequential bits or, inmodifications, a whole multiple of this, a new cycle begins with a newsynchronising signal S. In this form of construction, the pause signal Pat the beginning of a bit and the immediately following data signal D,lasts in each case for a sixth of the bit-time interval T. The energysignal E following the data signal D lasts for the remaining two thirdsof the bit-time interval T. Obviously, however, other divisions of thebit time interval T into the three different signals P, D and E of a bitare similarly in accordance with principles of the invention.

FIG. 7 shows the idealised voltage curve against time between the twoconductors 2, 3 of the bus 4 during the transmission of the last bit ofa cycle with a synchronising signal S. Instead of the normally occurringpause signal P as the beginning of the following bit, a synchronisingsignal S follows. The synchronising signal S marks the start of thefollowing cycle. The duration ΔT of the synchronising signal S amountsin this form of construction to a third of the Bit interval time T. Adifferent duration of this signal is similarly in accordance withprinciples of the invention.

The synchronising signal S is again followed by a first pause signal Pof the first bit in the new cycle, or, in the quoted modifications, of afirst pause signal P in the first cycle of a whole number of followingcycles. Each bit has a falling and rising edge. The falling edge, whichoccurs at the start of each pause signal P, defines the start of a newbit.

FIG. 8 shows the block circuit diagram of a form of construction of aBT, which is essentially the same for all BTs. In other words, the BT isessentially the same both for the master BT 1 and also for the remainingSlave BTs 5. The energy storage element 38 and its function have alreadybeen described under FIGS. 4 and 5, and are therefore not discussedhere.

Each BT includes an I/O port 26, a bus interface 28 or amaster-bus-interface 31, a time control and synchronising circuit 29,and an I/O configuration element 27. The I/O port 26, the bus interface28 or the master-bus-interface 31, the time control and synchronisingcircuit 29, and the I/O configuration element 27 are all connectedtogether and with the bus 4 in a suitable fashion. The I/O port 26 has anumber of parallel inputs and outputs. The number of theseinputs/outputs can in theory be specified as desired, but is however forpractical reasons typically a power of two (e.g., 2³).

If, for example, bytes each with 8 bits are to be transmitted, 8 of the1024 bits of a complete cycle are required, whereby a maximum possiblenumber of 1024/8=128 different addresses result in the BT. By settingthe configuration of the I/O configuration element 27, the 8 bits can beconfigured bitwise as a transmit or receive bit and also divided asdesired, for instance, into 1×2 bits and 1×6 bits, or also, similarly,for instance, into 2×4 bits, so that within a byte length, thetransmission of two 4-bit pieces of information is possible. The I/Oport 26 further includes the storage elements necessary for the storageof these 8 bits, as well as, in a modification, comparison elements forthe comparison of corresponding values D0-D7 from twoimmediately-following cycles.

These storage and comparison elements are not separately shown, sincethey correspond to the known state of the technology. In thismodification of the I/O port 26 via the I/O configuration element 27,for fault free transmission the elements are configured for doubledtransmission: a change of the values D0 to D7 is then only transmittedat the I/O port 26 following two cycles in which each correspondingvalue agrees.

The I/O port 26 is connected to the bus 4 via the bus interface 28, orvia the master bus interface 31. The time controlling and synchronisingcircuit 29 includes a time base 18, a bit counter 22, a byte counter 23,an address store 25, and a comparator 24. The time base 18, the bitcounter 22, the byte counter 23, the address store 25, and thecomparator 24 are similarly all interconnected and connected to the bus4 in a suitable fashion. In particular, the time base 18 is connectedvia the bus interface to the bus 4. The synchronising signal S presenton the bus 4 is captured by each slave BT 5 at the beginning of a cycleand the necessary reset 34 or master reset 35 signal is generated. Thetime base 18 associated withand the counter (i.e., the bit counter 22and the byte counter 23) connected to the reset signal are reset tonull. This process is further considered in the description under FIG.10.

Both the byte counter 23 and also the address store 25 are connected tothe comparator 24. The comparator 24 compares the freely pre-selectedaddress in the address store with the content of the byte counter 23. Ifthe contents of the freely pre-selected address in the address store andthe byte counter 23 agree, the next 8 bits on the bus 4 are transmittedto all the BTs with this specific address in the following time slotwhose duration corresponds to 8 bit time intervals T.

Whether these 8 bits are transmitted or received is controlled by thesimilarly pre-selected I.O configuration element 27. The address store25 and the I/O configuration element 27 can be realised using, forexample, DIP 8 switches, or by the circuit created by the positions ofvarious static short circuit plugs. At least one of the various shortcircuit plugs is decisive for the configuration of the BT as atransmitter or receiver. It is also in accordance with principles of theinvention to enter addresses or I/O configurations dynamically in amultiplex mode via at least one additional pin, which is available inall BTs, and to configure the BT as a transmitter or receiver. Theprocess of so dynamically entering addresses is well known to thespecialist.

FIG. 8 basically describes the construction of the master BT 1, which,however, as the directly supplied main station has no energy supplyelement 38. Further differences exist in the Bus Interface: the businterface 28 is replaced in the master BT 1 by the master bus interface31, which has already been discussed in the description of FIG. 3 andFIG. 4.

In FIG. 9, the detailed circuit diagram of a BT in the function ofmaster BT 1 is given. The master BT 1 includes a time base 18, whichincludes an internal oscillator 19, a clock divider 20, and an auxiliarycounter 21. The oscillator 19 operates for instance at a frequency of 1MHz. Obviously, in theory any other frequency is possible. The frequencyis determined by the choice of bit interval time T, the desired numberof possible addresses in the bus system, as well as by the desirednumber of bits per I/O port 26. In the clock divider 20, which followsthe oscillator 19 in the circuit, the frequency of the oscillator 19 is,for instance, halved five times (i.e., reduced to {fraction (1/32)} ofthe oscillator frequency). The number of frequency halvings depends onthe one hand on the oscillator frequency, and on the other on the bitfrequency aimed at on the bus 4.

The output of the clock divider 20 is applied to the input of theauxiliary counter 21. The auxiliary counter 21 has two alternativesettings: in the normal case of a customary bit it divides the frequencyof its input signal by 6. The periodic duration of the signal at itsoutput thus corresponds to the bit interval time T, as shown in FIG. 6.The output of the auxiliary counteroutput is connected to the input ofthe bit counter 22, which again divides the frequency of the signal atits input by 8.

The output of the bit counter 22 is applied to the input of the bytecounter 23, which divides the frequency of its input signal once more(here by 128). After running through a whole number of cycles, each of1024 bits, a logical 1 appears both at the further Most Significant Bitavailable output 37 of the bit counter and also at the further availableMost Significant Byte output 36 of the byte counter. These two outputs37 and 36 are connected to the inputs of an AND gate 30, which generatesthe logical product of these two inputs. The output of the AND gate 30is applied to a further input available on the auxiliary counter 21.

If a logical 1 appears at the further input, the auxiliary counter 21switches so that it no longer divides the frequency at its input by 6,but by 8. The duration of the period and thereby the duration of thisspecial bit is extended by the time interval ΔT. The output of theauxiliary counter 21 is connected to the master bus interface 31, whoseoutput is applied to conductor 2 of the bus 4. Thereby, following theenergy signal E, the synchronising signal S shown in FIG. 7, which couldalso be described as an energy signal E extended by the time intervalΔT, appears on the bus 4.

In FIG. 10 the detailed circuit diagram of a BT in the function of aslave BT 5 is presented, which has essentially the same elements as themaster BT 1. Differences from the master BT 1 consist of thefollowing: 1) instead of the master bus interface 31, a modified businterface 28, already described above, is used; and 2) each slave BT 5includes two further elements in addition to the elements mentioned inthe description of FIG. 9. These additional elements are a negative edgeend detector 33 and a bit length detector 32. The input of the negativeedge end detector 33 is connected to the bus interface 28 and generatesa Reset signal 34 at its output at the beginning of the pause signal Papplied to the bus 4.

Both the clock divider 20 and the auxiliary counter 21 have, as iscustomary in every counter, inputs via which these counters 20, 21 canbe reset to null. The output of the negative edge end detector 33 isconnected to these inputs. At the beginning of each bit, both the clockdivider 20 and the auxiliary counter 21 are reset to null in thismanner. Instead of the output of the auxiliary counter 21, the output ofthe negative edge end detector 33 is applied here to the bit counter 22and thereby effects a synchronous switching increase to the bit counter22 and the Byte counter 23, since the clock signal for the slaves istransmitted in the form of the negative edge via the bus 4.

The output of the auxiliary counter 21 is applied to the input of thebit length detector 32. The time base 18 is required here for timemeasurement, with the aid of which the bit length detector 32 determineswhether a normal bit or a bit extended by the synchronising signal S(i.e., a bit lengthened by the time interval ΔT) is present on the bus.If the latter is the case, the bit length detector 32 generates a masterreset signal 35 at its output. This output is connected to the inputsavailable both on the bit counter 22 and the byte counter 23, by whichthese counters 22, 23 can be reset. If, therefore, a synchronisingsignal S appears on the bus 4, in all the slave BTs 5 both the bitcounter 22 and also the byte counter 23 are reset to null.

Due to the largely-identical construction of the master BT 1 and theslave BT 5, in a modification, a basic form of a BT, which includes allthe components both of the master BT 1 and also of the slave BT 5, canbe put together using a few simultaneously operating switches, realisedelectronically or mechanically, thus switched as a master BT 1 or aslave BT 5, so that the currently not required elements are switchedout, and inputs and outputs of the different elements are assembled inthe desired form as described above.

It is obviously also in accordance with principles of the invention tointegrate a part or all of the components required for a BT onto asingle chip. This can, as is generally known, for instance, usingoperational amplifiers, be configured as master BT 1 or slave BT5, andeach used as a transmitter or receiver by the simplest externalcircuitry.

Due to the characteristics presented above, the bus system in accordancewith principles of the invention is especially suited to a multiplicityof applications, in which the transmission times do not need to beextremely short (e.g., they can even be in the order of magnitude ofhuman reaction times of some tenths of a second), while at the same timethe wiring outlay should be kept small. A typical example of this is thewiring of a ship: the transmission, for instance, of fuel level to adisplay, or the transmission of commands for the switching on or off ofmotors or other loads is not time critical as a rule in thisintrinsically sluggish system. Further typical examples are the wiringfor aircraft and vehicle electrical systems, for instance for thedisplay of closed conditions of doors, for the transmission of commandsfor the adjustment of lights, or for many similar purposes.

As a further application, a bus system in accordance with the inventioncan be applied for the control of lifts, and indeed both in the fixedand the moving selection stations. The great advantages as againstconventional controls are clear. But also in many simpler applications,as, for instance, in the wiring of house bells in a multi-family house,the use of the bus system in accordance with principles of the inventionpermits a reduction in the overall outlay, here for instance all thebell transformers can be saved and at the same time the wiring outlaymassively reduced.

What is claimed is:
 1. A device for controlling a bus, the devicecomprising: a three position switch, the three position switchcomprising a first input, a second input, a third input, and an outputconnectable to a bus; an energy receiving means connected to the firstinput, the second input, and the output; and a data switch connectedintermediate the second input and a null potential, the data switchhaving an open position and a closed position; wherein the third inputis connected to the null potential, and wherein a pause signal can beapplied at the output responsive to the three position switch being inthe third position, and wherein a first data bit can be applied at theoutput responsive to both the three position switch being in the secondposition and the data switch being in the open position, and wherein asecond data bit is applied at the output responsive to both the threeposition switch being in the second position and the data switch beingin the closed position, and wherein a synchronizing signal is applied atthe output responsive to the three position switch being in the thirdposition.
 2. The device of claim 1, wherein the output is furtherconfigurable to receive data responsive to the data switch being in theopen position.
 3. The device of claim 1, further comprising: a timecontroller connected to the three position switch; wherein the timecontroller is configured to control the three position switch.
 4. Thedevice of claim 1, further comprising: a direct current source connectedto the output.
 5. A device for controlling a bus, the device comprising:a three position switch, the three position switch comprising a firstinput, a second input, a third input, and an output connectable to abus; an energy receiving means connected to the first input, the secondinput, and the output, the energy receiving means for receiving energywith a first potential; and a data switch connected intermediate thesecond input and a second potential, the data switch having an openposition and a closed position; wherein a pause signal can be applied atthe output responsive to the three position switch being in the thirdposition, and wherein a first data bit can be applied at the outputresponsive to both the three position switch being in the secondposition and the data switch being in the open position, and wherein asecond data bit is applied at the output responsive to both the threeposition switch being in the second position and the data switch beingin the closed position, and wherein an energy signal is applied at theoutput responsive to the three position switch being in the thirdposition.
 6. The device of claim 5, wherein the output is furtherconfigurable to receive data responsive to the data switch being in theopen position.
 7. The device of claim 5, further comprising: a timecontroller connected to the three position switch; wherein the timecontroller is configured to control the three position switch.
 8. Thedevice of claim 5, wherein the second potential is a null potential.